The present invention relates to an on die termination (ODT) device and a semiconductor memory device including the same, and more particularly, to an on die termination device of a decreased size and a semiconductor memory device including the same.
Semiconductor devices are implemented into integrated circuit (IC) chips such as central processing units (CPUs), memories, and gate arrays, and are incorporated into a variety of electrical products such as personal computers, servers, and workstations. Most of semiconductor devices include an input circuit configured to receive signals from an outside world via input pads and an output circuit configured to provide internal signals to an outside world via output pads.
As the operating speed of electrical products is increasing, a swing width of a signal exchanged between semiconductor devices is being gradually reduced for minimizing a delay time taken for signal transmission. However, the reduction in the swing width of the signal has a great influence on an external noise, causing the signal reflectivity to be more critical at an interface terminal due to impedance mismatch. Such impedance mismatch is generally caused by an external noise, a variation of a power supply voltage, a change in an operating temperature, a change in a manufacturing process, etc. The impedance mismatch may lead to a difficulty in high-speed data transmission and distortion of output data. Therefore, if semiconductor devices receive the distorted output signal through an input terminal, problems such as a setup/hold failure and an error in decision of an input level may be frequently arisen.
In particular, in order to resolve the above problems, a memory device requiring high-speed performance employs an impedance matching circuit, which is called an ODT device, near an input pad inside an IC chip. In a typical ODT scheme, source termination is performed at a transmitting end by an output circuit, and parallel termination is performed at a receiving end by a termination circuit connected in parallel to a receiving circuit coupled to the input pad.
ZQ calibration refers to a procedure of generating pull-up and pull-down codes which are varied with process, voltage and temperature (PVT) conditions. The resistance of the ODT device, e.g., a termination resistance at a DQ pad in a memory device, is calibrated using the codes resulting from the ZQ calibration. The ZQ calibration is named because the calibration is performed using a ZQ node that is a node for calibration.
The ZQ calibration in the ODT device will be described below.
FIG. 1 is a circuit diagram of a conventional calibration circuit performing a ZQ calibration in an ODT device.
Referring to FIG. 1, the conventional ODT device includes a first calibration resistance unit 110, second calibration resistance units 120 and 130, a reference voltage generation unit 102, comparing units 103 and 104, and counting units 105 and 106 to perform the ZQ calibration. The ZQ calibration is enabled by an operation control unit 107 and a counting unit 108.
The first calibration resistance unit 110 includes a plurality of pull-up resistors which are turned on/off in response to pull-up calibration codes PCODE<0:N>. The second calibration resistance units 120 and 130 include a pull-up calibration resistance unit 120 and a pull-down calibration resistance unit 130. The pull-up calibration resistance unit 120 has the same configuration as the first calibration resistance unit 110. The pull-down calibration resistance unit 130 includes a plurality of pull-down resistors which are turned on/off in response to pull-down calibration codes NCODE<0:N>.
The first calibration resistance unit 110 is calibrated with an external resistor 101 connected to a ZQ node to generate primary calibration codes, pull-up calibration codes PCODE<0:N>. The second calibration resistance units 120 and 130 generates secondary calibration codes, pull-down calibration codes NCODE<0:N> using the primary calibration codes PCODE<0:N>.
The comparing unit 103 compares a voltage of the ZQ node and a reference voltage VREF to generate an up signal UP and a down signal DOWN. The voltage of the ZQ node is generated by connecting the first calibration resistance unit 110 and the external resistor 101 of generally 240Ω. Here, the external resistor 101 is connected to a ZQ pin that is an external chip surface of the ZQ node. The reference voltage is generated by an internal reference voltage generation unit 102, and is generally set to VDDQ/2.
The pull-up counter 105 receives the up/down signals to generate binary codes, the pull-up codes PCODE<0:N>. The generated binary codes, i.e., the pull-up calibration codes PCODE<0:N> are used for turning on/off resistors connected in parallel in the first calibration resistance unit 110 to control resistance of the first calibration resistance unit 110. The controlled resistance of the first calibration resistance unit 110 is reflected again in the ZQ node voltage, and then the above described operation is repeated. That is, the first calibration resistance unit 110 is calibrated such that a total resistance of the first calibration resistance unit 110 becomes identical to that of the external resistor 101 of generally 240Ω (pull-up calibration).
The binary codes, i.e., the pull-up calibration code PCODE<0:N> generated by the above described pull-up calibration are input to the pull-up calibration resistance unit 120 to determine the total resistance of the pull-up calibration resistance unit 120. Next, a pull-down calibration is performed in a similar manner to the pull-up calibration, using the comparing unit 104 and the pull-down counting unit 106. Through the pull-down calibration, a voltage of node A becomes identical to the reference voltage VREF, that is, a total resistance of the pull-down calibration resistance unit 130 becomes identical to the total resistance of the pull-up calibration resistance unit 120.
The binary codes, i.e., the pull-up calibration codes PCODE<0:N> and the pull-down calibration codes NCODE<0:N> resulting from the above described ZQ calibrations, including the pull-up and pull-down calibrations, are input to termination resistors, including pull-up and pull-down resistors, at input/output pads. Resultantly, a resistance of the ODT device, e.g., pull-up and pull-down termination resistances at a DQ pad in a memory device, is determined. For reference, the pull-up and pull-down resistors at the input/output pads have identical layouts to the pull-up and pull-down calibration resistance units 120 and 130 of the calibration circuit shown in FIG. 1.
Enabling the ZQ calibration, i.e., enabling the calibration circuit is determined by the operation control unit 107 and the counting unit 108. The operation control unit 107 receives input signals ZQC, RESETB and A<10> and outputs signals ZQINIT, ZQOPER, ZQCS to select the kind of ZQ calibrations to be performed. Different types of ZQ calibration have different calibration times. The counting unit 108 counts a clock CLK to enable the comparing units 103 and 104 for a predetermined duration for each kind of ZQ calibrations to perform the ZQ calibration.
FIG. 2 is a circuit diagram illustrating a method for determining a termination resistance of an output driver in a semiconductor memory device using the calibration codes PCODE<0:N> and NCODE<0:N> generated by the calibration circuit of FIG. 1.
The output driver serves to output data in the semiconductor memory device. Referring to FIG. 2, the output driver includes pull-up and pull-down pre-driver units 210 and 220, and pull-up and pull-down termination resistance units 230 and 240 for outputting data. Pull-up and pull-down termination resistance units 230 and 240 are supplied with drain and source voltages VDDQ and VSSQ respectively.
A simple operation of the output driver will be described below. The pull-up and pull-down pre-driver units 210 and 220 control the pull-up termination resistance units 230 and 240, respectively. To output a data of a logic high level, the pull-up termination resistance unit 230 is turned on so that a data pin DQ has a logic high state. To output a data of a logic low level, the pull-down termination resistance unit 240 is turned on so that the data pin DQ has a logic low state. That is, by performing pull-up termination or pull-down termination, logic high level data or a logic low level data can be output.
Here, the number of resistors to be turned on in the pull-up termination resistance units 230 and the pull-down resistance unit 240 is determined by the pull-up calibration codes PCODE<0:N> and the pull-down calibration codes NCODE<0:N>. That is, which of the pull-up termination resistance unit 230 and the pull-down termination resistance unit 240 is to be turned on is determined by the logic state of the output data. However, the resistors to be turned on in the termination resistance units 230 and 240 are selected by the calibration codes PCODE<0:N> and NCODE<0:N>.
For reference, target resistances of the pull-up termination resistance unit 230 and the pull-down termination resistance unit are not necessarily identical to the resistance of 240Ω of the calibration resistance units 110, 120 and 130 in FIG. 1. For example, the target resistances thereof may also be ½ or ¼ of 240Ω, i.e., 120Ω or 60Ω. Signals DQP_CTRL and DQN_CTRL input to the pre-driver units 210 and 220 represents a group of control signals.
FIG. 3 is a block diagram of a conventional ODT device for illustrating transfer of codes generated in the calibration circuit of FIG. 1 to the termination resistance circuit, i.e., the output driver shown in FIG. 2.
The calibration circuit 310 generates a pull-up calibration code PCODE<0:N> and a pull-down calibration code NCODE<0:N>. The calibration codes PCODE<0:N> and NCODE<0:N> are transferred to the termination resistance circuit, i.e., the output driver 320 through a metal line connecting the calibration circuit 310 and the output driver 320. Since the total number of the pull-up and pull-down calibration codes PCODE<0:N> and NCODE<0:N> is 2(N+1), 2(N+1) metal lines are required. The distance between the calibration circuit 310 near around the ZQ pad and the output driver 320 near around the DQ pad is extremely long relatively in the semiconductor memory device. Therefore, connecting such a long distance with 2(N+1) metal lines may extremely increase a chip size.